mirror of
https://git.eden-emu.dev/eden-emu/eden.git
synced 2026-06-06 01:13:45 -04:00
[dynarmic,loongarch] addressing Lizzie comments
This commit is contained in:
Yang Liu
crueter
parent
dab20371a2
commit
429a7f6fe9
4 changed files with 95 additions and 93 deletions
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@ -20,7 +20,7 @@ public:
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explicit CodeBlock(std::size_t size) noexcept
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: memsize(size) {
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mem = static_cast<u8*>(mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0));
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ASSERT(mem != nullptr);
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ASSERT(mem != MAP_FAILED);
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la_init_assembler(&as, mem, size);
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}
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@ -37,10 +37,10 @@ struct Relocation {
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};
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struct EmittedBlockInfo {
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std::vector<Relocation> relocations;
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CodePtr entry_point;
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size_t size;
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size_t cycle_count;
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std::vector<Relocation> relocations;
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};
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struct EmitConfig {};
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@ -5,6 +5,7 @@
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#include <algorithm>
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#include <array>
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#include <limits>
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#include "dynarmic/backend/loongarch64/lagoon_cpp.h"
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@ -82,7 +83,7 @@ void HostLocInfo::SetupScratchLocation() {
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}
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bool HostLocInfo::IsCompletelyEmpty() const {
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return values.empty() && !locked && !realized && !accumulated_uses && !expected_uses && !uses_this_inst;
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return values.empty() && !locked && !accumulated_uses && !expected_uses && !uses_this_inst && !realized;
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}
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void HostLocInfo::UpdateUses() {
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@ -97,7 +98,7 @@ void HostLocInfo::UpdateUses() {
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}
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RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
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ArgumentInfo ret = {Argument{*this}, Argument{*this}, Argument{*this}, Argument{*this}};
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ArgumentInfo ret = {Argument{}, Argument{}, Argument{}, Argument{}};
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for (size_t i = 0; i < inst->NumArgs(); i++) {
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const IR::Value arg = inst->GetArg(i);
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ret[i].value = arg;
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@ -114,14 +115,8 @@ bool RegAlloc::IsValueLive(IR::Inst* inst) const {
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}
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void RegAlloc::UpdateAllUses() {
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for (auto& gpr : gprs) {
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gpr.UpdateUses();
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}
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for (auto& fpr : fprs) {
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fpr.UpdateUses();
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}
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for (auto& spill : spills) {
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spill.UpdateUses();
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for (auto& info : hostloc_info) {
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info.UpdateUses();
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}
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}
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@ -141,17 +136,15 @@ void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
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void RegAlloc::AssertNoMoreUses() const {
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// TODO: Re-enable this assert once all register allocation issues are fixed
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// const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); };
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// ASSERT(std::all_of(gprs.begin(), gprs.end(), is_empty));
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// ASSERT(std::all_of(fprs.begin(), fprs.end(), is_empty));
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// ASSERT(std::all_of(spills.begin(), spills.end(), is_empty));
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// ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), is_empty));
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}
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template<HostLoc::Kind kind>
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u32 RegAlloc::GenerateImmediate(const IR::Value& value) {
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if constexpr (kind == HostLoc::Kind::Gpr) {
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const u32 new_location_index = AllocateRegister(gprs, gpr_order);
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const u32 new_location_index = AllocateRegister(gpr_order, GprOffset);
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SpillGpr(new_location_index);
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gprs[new_location_index].SetupScratchLocation();
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hostloc_info[GprOffset + new_location_index].SetupScratchLocation();
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la_load_immediate64(&as, static_cast<la_gpr_t>(new_location_index),
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static_cast<int64_t>(value.GetImmediateAsU64()));
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@ -183,7 +176,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
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ASSERT(!ValueInfo(*current_location).locked);
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if constexpr (required_kind == HostLoc::Kind::Gpr) {
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const u32 new_location_index = AllocateRegister(gprs, gpr_order);
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const u32 new_location_index = AllocateRegister(gpr_order, GprOffset);
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SpillGpr(new_location_index);
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switch (current_location->kind) {
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@ -199,11 +192,11 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
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break;
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}
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gprs[new_location_index] = std::exchange(ValueInfo(*current_location), {});
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gprs[new_location_index].realized = true;
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hostloc_info[GprOffset + new_location_index] = std::exchange(ValueInfo(*current_location), {});
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hostloc_info[GprOffset + new_location_index].realized = true;
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return new_location_index;
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} else if constexpr (required_kind == HostLoc::Kind::Fpr) {
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const u32 new_location_index = AllocateRegister(fprs, fpr_order);
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const u32 new_location_index = AllocateRegister(fpr_order, FprOffset);
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SpillFpr(new_location_index);
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switch (current_location->kind) {
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@ -219,27 +212,26 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
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break;
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}
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fprs[new_location_index] = std::exchange(ValueInfo(*current_location), {});
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fprs[new_location_index].realized = true;
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hostloc_info[FprOffset + new_location_index] = std::exchange(ValueInfo(*current_location), {});
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hostloc_info[FprOffset + new_location_index].realized = true;
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return new_location_index;
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} else {
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UNREACHABLE();
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}
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}
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template<HostLoc::Kind required_kind>
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u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
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u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value, HostLoc::Kind required_kind) {
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if (value == nullptr) {
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// Scratch register allocation
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if constexpr (required_kind == HostLoc::Kind::Gpr) {
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const u32 idx = AllocateRegister(gprs, gpr_order);
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if (required_kind == HostLoc::Kind::Gpr) {
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const u32 idx = AllocateRegister(gpr_order, GprOffset);
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SpillGpr(idx);
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gprs[idx].SetupScratchLocation();
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hostloc_info[GprOffset + idx].SetupScratchLocation();
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return idx;
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} else if constexpr (required_kind == HostLoc::Kind::Fpr) {
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const u32 idx = AllocateRegister(fprs, fpr_order);
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} else if (required_kind == HostLoc::Kind::Fpr) {
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const u32 idx = AllocateRegister(fpr_order, FprOffset);
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SpillFpr(idx);
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fprs[idx].SetupScratchLocation();
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hostloc_info[FprOffset + idx].SetupScratchLocation();
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return idx;
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}
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}
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@ -254,15 +246,15 @@ u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
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info.expected_uses = value->UseCount();
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};
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if constexpr (required_kind == HostLoc::Kind::Gpr) {
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const u32 new_location_index = AllocateRegister(gprs, gpr_order);
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if (required_kind == HostLoc::Kind::Gpr) {
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const u32 new_location_index = AllocateRegister(gpr_order, GprOffset);
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SpillGpr(new_location_index);
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setup_location(gprs[new_location_index]);
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setup_location(hostloc_info[GprOffset + new_location_index]);
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return new_location_index;
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} else if constexpr (required_kind == HostLoc::Kind::Fpr) {
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const u32 new_location_index = AllocateRegister(fprs, fpr_order);
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} else if (required_kind == HostLoc::Kind::Fpr) {
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const u32 new_location_index = AllocateRegister(fpr_order, FprOffset);
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SpillFpr(new_location_index);
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setup_location(fprs[new_location_index]);
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setup_location(hostloc_info[FprOffset + new_location_index]);
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return new_location_index;
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} else {
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UNREACHABLE();
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@ -271,61 +263,79 @@ u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
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template u32 RegAlloc::RealizeReadImpl<HostLoc::Kind::Gpr>(const IR::Value& value);
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template u32 RegAlloc::RealizeReadImpl<HostLoc::Kind::Fpr>(const IR::Value& value);
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template u32 RegAlloc::RealizeWriteImpl<HostLoc::Kind::Gpr>(const IR::Inst* value);
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template u32 RegAlloc::RealizeWriteImpl<HostLoc::Kind::Fpr>(const IR::Inst* value);
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u32 RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const std::vector<u32>& order) const {
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const auto empty = std::find_if(order.begin(), order.end(), [&](u32 i) { return regs[i].values.empty() && !regs[i].locked; });
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u32 RegAlloc::AllocateRegister(const std::vector<u32>& order, size_t base_offset) {
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const auto empty = std::find_if(order.begin(), order.end(), [&](u32 i) {
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auto& info = hostloc_info[base_offset + i];
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return info.values.empty() && !info.locked;
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});
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if (empty != order.end()) {
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return *empty;
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}
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std::vector<u32> candidates;
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std::copy_if(order.begin(), order.end(), std::back_inserter(candidates), [&](u32 i) { return !regs[i].locked; });
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std::copy_if(order.begin(), order.end(), std::back_inserter(candidates), [&](u32 i) {
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return !hostloc_info[base_offset + i].locked;
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});
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ASSERT(!candidates.empty());
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// TODO: LRU
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std::uniform_int_distribution<size_t> dis{0, candidates.size() - 1};
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return candidates[dis(rand_gen)];
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u32 best = candidates[0];
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size_t min_lru = hostloc_info[base_offset + best].lru_counter;
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for (size_t i = 1; i < candidates.size(); ++i) {
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auto& info = hostloc_info[base_offset + candidates[i]];
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if (info.lru_counter < min_lru) {
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min_lru = info.lru_counter;
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best = candidates[i];
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}
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}
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hostloc_info[base_offset + best].lru_counter++;
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return best;
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}
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void RegAlloc::SpillGpr(u32 index) {
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ASSERT(!gprs[index].locked && !gprs[index].realized);
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if (gprs[index].values.empty()) {
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auto& gpr_info = hostloc_info[GprOffset + index];
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ASSERT(!gpr_info.locked && !gpr_info.realized);
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if (gpr_info.values.empty()) {
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return;
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}
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const u32 new_location_index = FindFreeSpill();
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la_st_d(&as, static_cast<la_gpr_t>(index), LA_SP,
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static_cast<int32_t>(spill_offset + new_location_index * spill_slot_size));
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spills[new_location_index] = std::exchange(gprs[index], {});
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hostloc_info[SpillOffset + new_location_index] = std::exchange(gpr_info, {});
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}
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void RegAlloc::SpillFpr(u32 index) {
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ASSERT(!fprs[index].locked && !fprs[index].realized);
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if (fprs[index].values.empty()) {
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auto& fpr_info = hostloc_info[FprOffset + index];
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ASSERT(!fpr_info.locked && !fpr_info.realized);
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if (fpr_info.values.empty()) {
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return;
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}
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const u32 new_location_index = FindFreeSpill();
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la_fst_d(&as, static_cast<la_fpr_t>(index), LA_SP,
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static_cast<int32_t>(spill_offset + new_location_index * spill_slot_size));
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spills[new_location_index] = std::exchange(fprs[index], {});
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hostloc_info[SpillOffset + new_location_index] = std::exchange(fpr_info, {});
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}
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u32 RegAlloc::FindFreeSpill() const {
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const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); });
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ASSERT(iter != spills.end() && "All spill locations are full");
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return static_cast<u32>(iter - spills.begin());
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for (size_t i = 0; i < SpillCount; ++i) {
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if (hostloc_info[SpillOffset + i].values.empty()) {
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return static_cast<u32>(i);
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}
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}
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UNREACHABLE();
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}
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std::optional<HostLoc> RegAlloc::ValueLocation(const IR::Inst* value) const {
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const auto contains_value = [value](const HostLocInfo& info) {
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return info.Contains(value);
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};
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if (const auto iter = std::find_if(gprs.begin(), gprs.end(), contains_value); iter != gprs.end()) {
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return HostLoc{HostLoc::Kind::Gpr, static_cast<u32>(iter - gprs.begin())};
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} else if (const auto iter = std::find_if(fprs.begin(), fprs.end(), contains_value); iter != fprs.end()) {
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return HostLoc{HostLoc::Kind::Fpr, static_cast<u32>(iter - fprs.begin())};
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} else if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != spills.end()) {
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return HostLoc{HostLoc::Kind::Spill, static_cast<u32>(iter - spills.begin())};
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for (size_t i = 0; i < hostloc_info.size(); ++i) {
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if (hostloc_info[i].Contains(value)) {
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if (i < GprCount) {
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return HostLoc{HostLoc::Kind::Gpr, static_cast<u32>(i)};
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} else if (i < GprCount + FprCount) {
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return HostLoc{HostLoc::Kind::Fpr, static_cast<u32>(i - GprCount)};
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} else {
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return HostLoc{HostLoc::Kind::Spill, static_cast<u32>(i - GprCount - FprCount)};
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}
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}
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}
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return std::nullopt;
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}
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@ -333,25 +343,20 @@ std::optional<HostLoc> RegAlloc::ValueLocation(const IR::Inst* value) const {
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HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
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switch (host_loc.kind) {
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case HostLoc::Kind::Gpr:
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return gprs[size_t(host_loc.index)];
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return hostloc_info[GprOffset + host_loc.index];
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case HostLoc::Kind::Fpr:
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return fprs[size_t(host_loc.index)];
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return hostloc_info[FprOffset + host_loc.index];
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case HostLoc::Kind::Spill:
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return spills[size_t(host_loc.index)];
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return hostloc_info[SpillOffset + host_loc.index];
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}
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UNREACHABLE();
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}
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HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
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const auto contains_value = [value](const HostLocInfo& info) {
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return info.Contains(value);
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};
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if (const auto iter = std::find_if(gprs.begin(), gprs.end(), contains_value); iter != gprs.end()) {
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return *iter;
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} else if (const auto iter = std::find_if(fprs.begin(), fprs.end(), contains_value); iter != fprs.end()) {
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return *iter;
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} else if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != spills.end()) {
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return *iter;
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for (auto& info : hostloc_info) {
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if (info.Contains(value)) {
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return info;
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}
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}
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UNREACHABLE();
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}
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@ -5,7 +5,6 @@
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#include <array>
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#include <optional>
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#include <random>
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#include <utility>
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#include <vector>
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@ -73,12 +72,10 @@ public:
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private:
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friend class RegAlloc;
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explicit Argument(RegAlloc& reg_alloc)
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: reg_alloc{reg_alloc} {}
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explicit Argument() {}
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bool allocated = false;
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RegAlloc& reg_alloc;
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IR::Value value;
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bool allocated = false;
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};
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template<typename T>
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@ -111,10 +108,11 @@ private:
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struct HostLocInfo final {
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std::vector<const IR::Inst*> values;
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size_t locked = 0;
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bool realized = false;
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size_t uses_this_inst = 0;
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size_t accumulated_uses = 0;
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size_t expected_uses = 0;
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bool realized = false;
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size_t lru_counter = 0;
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bool Contains(const IR::Inst*) const;
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void SetupScratchLocation();
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@ -127,7 +125,7 @@ public:
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using ArgumentInfo = std::array<Argument, IR::max_arg_count>;
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explicit RegAlloc(lagoon_assembler_t& as, std::vector<u32> gpr_order, std::vector<u32> fpr_order)
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: as{as}, gpr_order{gpr_order}, fpr_order{fpr_order}, rand_gen{std::random_device{}()} {}
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: as{as}, gpr_order{std::move(gpr_order)}, fpr_order{std::move(fpr_order)} {}
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ArgumentInfo GetArgumentInfo(IR::Inst* inst);
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bool IsValueLive(IR::Inst* inst) const;
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@ -146,8 +144,6 @@ public:
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void DefineAsExisting(IR::Inst* inst, Argument& arg);
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void SpillAll();
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template<typename... Ts>
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static void Realize(Ts&... rs) {
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static_assert((mcl::is_instance_of_template<RAReg, Ts>() && ...));
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@ -165,10 +161,9 @@ private:
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u32 GenerateImmediate(const IR::Value& value);
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template<HostLoc::Kind kind>
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u32 RealizeReadImpl(const IR::Value& value);
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template<HostLoc::Kind kind>
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u32 RealizeWriteImpl(const IR::Inst* value);
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u32 RealizeWriteImpl(const IR::Inst* value, HostLoc::Kind required_kind);
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u32 AllocateRegister(const std::array<HostLocInfo, 32>& regs, const std::vector<u32>& order) const;
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u32 AllocateRegister(const std::vector<u32>& order, size_t base_offset);
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void SpillGpr(u32 index);
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void SpillFpr(u32 index);
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u32 FindFreeSpill() const;
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@ -181,11 +176,13 @@ private:
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std::vector<u32> gpr_order;
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std::vector<u32> fpr_order;
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std::array<HostLocInfo, 32> gprs;
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std::array<HostLocInfo, 32> fprs;
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||||
std::array<HostLocInfo, SpillCount> spills;
|
||||
static constexpr size_t GprCount = 32;
|
||||
static constexpr size_t FprCount = 32;
|
||||
static constexpr size_t GprOffset = 0;
|
||||
static constexpr size_t FprOffset = GprCount;
|
||||
static constexpr size_t SpillOffset = GprCount + FprCount;
|
||||
|
||||
mutable std::mt19937 rand_gen;
|
||||
std::array<HostLocInfo, GprCount + FprCount + SpillCount> hostloc_info;
|
||||
};
|
||||
|
||||
template<typename T>
|
||||
|
|
@ -226,9 +223,9 @@ RAReg<T>::~RAReg() {
|
|||
template<typename T>
|
||||
void RAReg<T>::Realize() {
|
||||
if (write && value.IsEmpty()) {
|
||||
reg = T{reg_alloc.RealizeWriteImpl<kind>(nullptr)};
|
||||
reg = T{reg_alloc.RealizeWriteImpl(nullptr, kind)};
|
||||
} else {
|
||||
reg = T{write ? reg_alloc.RealizeWriteImpl<kind>(value.GetInst()) : reg_alloc.RealizeReadImpl<kind>(value)};
|
||||
reg = T{write ? reg_alloc.RealizeWriteImpl(value.GetInst(), kind) : reg_alloc.RealizeReadImpl<kind>(value)};
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue