From 4c9ea4d25806625a1a4778be71b80ab4c4e10009 Mon Sep 17 00:00:00 2001
From: rayman30 <silentbitdev@gmail.com>
Date: Fri, 30 Jan 2026 01:48:06 +0100
Subject: [PATCH] dynarmic: Implement VectorMin/Max{S,U}64 emitters

Implements the missing A64 backend emitters for VectorMinS64, VectorMinU64, VectorMaxS64, and VectorMaxU64.

These IR opcodes are generated by the optimizer but lack direct hardware instruction support for 64-bit elements in the base NEON set (e.g., UMIN.2D does not exist). They are implemented using a compare (CMGT/CMHI) followed by a bitwise select (BSL). This correctly selects between the two source registers, whereas using BIT would incorrectly zero out elements.

Unit tests could not be added to a64.cpp because UMIN.2D is not a valid A64 instruction, causing the assembler (Oaknut) to reject it. The fix was verified by running Team Sonic Racing on macOS (Apple Silicon), which previously crashed on this synthetic opcode.

Fixes crash in Team Sonic Racing.
---
 .../backend/arm64/emit_arm64_vector.cpp       | 32 +++++++++----------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
index 6ac8531bfc..d575cd66ee 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
@@ -866,10 +866,10 @@ void EmitIR<IR::Opcode::VectorMaxS32>(oaknut::CodeGenerator& code, EmitContext&
 
 template<>
 void EmitIR<IR::Opcode::VectorMaxS64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    UNREACHABLE();
+    EmitThreeOp(code, ctx, inst, [&](auto& Qresult, auto& Qa, auto& Qb) {
+        code.CMGT(Qresult->D2(), Qa->D2(), Qb->D2());
+        code.BSL(Qresult->B16(), Qa->B16(), Qb->B16());
+    });
 }
 
 template<>
@@ -889,10 +889,10 @@ void EmitIR<IR::Opcode::VectorMaxU32>(oaknut::CodeGenerator& code, EmitContext&
 
 template<>
 void EmitIR<IR::Opcode::VectorMaxU64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    UNREACHABLE();
+    EmitThreeOp(code, ctx, inst, [&](auto& Qresult, auto& Qa, auto& Qb) {
+        code.CMHI(Qresult->D2(), Qa->D2(), Qb->D2());
+        code.BSL(Qresult->B16(), Qa->B16(), Qb->B16());
+    });
 }
 
 template<>
@@ -912,10 +912,10 @@ void EmitIR<IR::Opcode::VectorMinS32>(oaknut::CodeGenerator& code, EmitContext&
 
 template<>
 void EmitIR<IR::Opcode::VectorMinS64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    UNREACHABLE();
+    EmitThreeOp(code, ctx, inst, [&](auto& Qresult, auto& Qa, auto& Qb) {
+        code.CMGT(Qresult->D2(), Qb->D2(), Qa->D2());
+        code.BSL(Qresult->B16(), Qa->B16(), Qb->B16());
+    });
 }
 
 template<>
@@ -935,10 +935,10 @@ void EmitIR<IR::Opcode::VectorMinU32>(oaknut::CodeGenerator& code, EmitContext&
 
 template<>
 void EmitIR<IR::Opcode::VectorMinU64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    UNREACHABLE();
+    EmitThreeOp(code, ctx, inst, [&](auto& Qresult, auto& Qa, auto& Qb) {
+        code.CMHI(Qresult->D2(), Qb->D2(), Qa->D2());
+        code.BSL(Qresult->B16(), Qa->B16(), Qb->B16());
+    });
 }
 
 template<>